A Stationary Converging Self Interference Mitigating Approach for Full-Duplex MIMO Relays

A Stationary Converging Self Interference Mitigating Approach for Full-Duplex MIMO Relays
Authors:REVATHI, V.UMA

Abstract: Relaying is used in wireless communication, relay nodes are using in relaying process. Relay node are receiving the information from source node while transmitting to destination node. Full-duplex relaying is more spectrally efficient than the half-duplex relaying. Multiple users can communicate each other by using MIMO. This work proposes an adaptive method to mitigate the self-interference signal for full-duplex decode-and-forward MIMO relays which is able to track temporal variations of the self-interference channel. This method makes use of signals available at the relay to estimate the self-interference channel in order to cancel it. Further it analyzes the behavior of the algorithm in terms of its stationary points and mean convergence. The proposed cancellation block can be added to a full-duplex relay, if the self-interference is too large in its current operation environment. 

Keywords: Full-Duplex, Regenerative Relaying, Self-Interference, MIMO, Adaptive Filtering. 

INTRODUCTION 

          Full duplex (FD) wireless systems have the potential to double the system spectral efficiency compared to half duplex(HD) systems [1]. The main difficulty in implementing a FD system is that the strong loop-back selfinterference exceeds the limited dynamic range at the receiver. This phenomenonis critical since it saturates the receiver which will not only prevent the correct reception of the desired signal but may also damage the device. Recently, several approaches have been proposed to implement SISO FD transceivers via self-interference cancellation. Most of them involve advanced concepts in both RF transceiver architecture and digital signal processing at the receiver. The simplest approach is to use directional transmit (Tx) and receive (Rx) antennas to decouple the Tx and Rx signals [2]. However, this approach is only suitable when the data source and the data sink are sufficiently separated spatially (probably different devices). In [3], an antenna cancellation approach was proposed, which requires two Tx antennas. By proper position adjustment, the signals of both Tx antennas overlap destructively at the Rx antenna, which leads to a certain degree of self-interference cancellation. This approach can be regarded as a static beam-forming approach and has the drawback that it is only suitable for narrow band transmissions and requires accurate manual tuning of antenna positions.

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Time and Power Optimized Enhanced Serial Communication Links for High Throughput Applications

Time and Power Optimized Enhanced Serial Communication Links for High Throughput Applications
Authors:SAROJA, DR.V.SAILAJA

Abstract: This paper proposes embedded transition inversion (ETI) to reduce bit transitions in serializing parallel buses, implies reduction in power. This paper proposes an embedded transition inversion (ETI) coding scheme that uses the phase difference between the clock and data in the transmitted serial data to tackle the problem of the extra indication bit. The technique is implemented in an optimized fashion using pipelining so that it can be used in practical systems with only a slight compromise in performance. This is achieved by calculating the decision as the data is being loaded on to the buffer and doing the encoding on the fly. This is one aspect which is lacking in most existing algorithms as they are not amenable to low delay implementation. 

Keywords: Embedded Transition Inversion (ETI), (Transition Inversion Coding) TIC, Phase Encoding, Tackle, B2I (Bit2invertion), Buffer, Serialized Buffer, Pipelining, Optimization. 

INTRODUCTION 

          Low power design, in a system perspective, happens at all levels of the digital electronic system stack. It is being done from the lowermost device level design to the topmost software design. And there are the intermediate levels where a lot of effort is being expended to make systems run at low power, keeping the compromise in performance to be minimum. The increasing density of the integrated circuits as postulated by Moore’s law makes it even more important to have low power systems since the power supply for such a dense integrated circuit may not keep track in size with the miniaturization of the electronic components. Hence research is being made at all levels of a system stack. A system can consist of multiple components. 

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An Enhanced and Low Power Communication System using ETI

An Enhanced and Low Power Communication System using ETI
Authors:P.V.S.N.SATHEESH KUMAR, B.MALLESWARI

Abstract: Here, in this project; embedded transition inversion (ETI) is proposed to reduce bit transitions in Serializing parallel buses. Implies power can be reduced further. This project proposes an embedded transition inversion (ETI) coding scheme that uses the phase difference between the clock and data in the transmitted serial data to tackle the problem of the extra indication bit. The technique is implemented in an optimized fashion using pipelining so that it can be used in practical systems with only a slight compromise in performance. This is achieved by calculating the decision as the data is being loaded on to the buffer and doing the encoding on the fly. This is one aspect which is lacking in most existing algorithms as they are not amenable to low delay implementation. As an enhancement B2I block is eliminated by using master slave flip-flop. Bit2 inversion output is yielded without using B2I block. Furthermore area can be reduced with this enhancement. 

Keywords: ETI, TIC, Phase Encoding, Tackle, B2I, Buffer, Serialized Buffer, Pipelining, and Optimization. 

 INTRODUCTION 

            Low power design, in a system perspective, happens at all levels of the digital electronic system stack. It is being done from the lowermost device level design to the topmost software design. And there are the intermediate levels where a lot of effort is being expended to make systems run at low power, keeping the compromise in performance to be minimum. The increasing density of the integrated circuits as postulated by Moore’s law makes it even more important to have low power systems since the power supply for such a dense integrated circuit may not keep track in size with the miniaturization of the electronic components. Hence research is being made at all levels of a system stack. A system can consist of multiple components. They can be broadly classified and a communication framework designed work.

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VLSI Implementation of ALU using Reversible Logic with Vedic Mathematics

VLSI Implementation of ALU using Reversible Logic with Vedic Mathematics
Authors:SRAVANTHI, T.VENKATA LAKSHMI

Abstract: High speed and power efficient ALU plays a vital role in microcontrollers, microprocessors, central processing units. In CPU one of the most important blocks is arithmetic and logic unit hence it is requisite to have fast and efficient ALU. Information lossless (or) reversible circuits have applications in communications, digital signal processing, and computer graphics. Reversible logic is used to reduce the power dissipation that occurs in normal circuits by preventing the loss of information. In this paper arithmetic and logical unit designed by using reversible logic with Vedic mathematics. This ALU is not only efficient in power and speed but also in area. In arithmetic unit basic operations are addition, subtraction, multiplication among these operations multiplication plays major role in ALU the speed of the ALU will depends upon the speed of the multiplier. There are so many multiplier techniques among that Vedic Urdhva Tiryakbhayam algorithm is best one it generates partial products parallel and concurrent addition of these partial prodect is done. All the modules are designed by using reversible gates. This ALU is able to perform four arithmetic and 16 logical operations. The proposed arithmetic and logical unit is coded in Verilog HDL synthesized and simulated using XilinxISE software. 

Keywords: ALU, UT Technique, Subtractor, Comparator, Area. 

 INTRODUCTION 

          ALU is a complex arithmetic structure, which is reflected in its moderately more signal propagation delay, more power dissipation, and high area requirement. When choosing a ALU for a digital system, the bit width of the ALU is required to be at least as wide as the largest operand of the applications that are to be executed on that digital system. The digital ALU is a ubiquitous arithmetic unit in microprocessors, digital signal processors, and emerging media processors [2]–[3]. It is also a kernel operator in application specific data path of video and audio codecs, digital filters, computer graphics, and embedded systems [6]–[9]. Com- pared with many other arithmetic operations, multiplication is time-consuming and power hungry. The critical paths dominated by digital multipliers often impose a speed limit on the entire design. Hence, VLSI design of high-speed multipliers, with low energy dissipation, is still a popular research subject. Now a day‟s all CPU units, any machinery parts utilizes a basic arithmetic operations like addition, subtraction, multiplications. ALU plays a vital role in CPU‟s, Microprocessors, Microcontrollers so ALU is the heart of the processor. The central processing unit speed is greately depends upon the ALU so we need to have fast and efficient ALU.

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A Virus Detection Process for Embedded Network Security with Low Power Consumption

A Virus Detection Process for Embedded Network Security with Low Power Consumption
Authors:G.S.SIVA KUMAR, G.SNEHITHA

Abstract: In this project, an adaptively dividable dual-port BiTCAM (unifying binary and ternary CAMs) is proposed to achieve a high-throughput, low-power, and low-cost virus-detection processor for mobile devices. The proposed dual-port BiTCAM is realized with the dual-port AND-type match-line scheme which is composed of dual-port dynamic AND gates. The dual-port designs reduce power consumption and increase storage efficiency due to shared storage spaces. Network security for mobile devices is in high demand because of the increasing virus count. Since mobile devices have limited CPU power, dedicated hardware is required, which will be yield by our BitCAM technique is essential to provide sufficient virus detection performance. 

Keywords: Ternary, Dual port, Virus, Unifying, CAM, Dynamic Power, Exactly Matching Engine. 

 INTRODUCTION 

              In this project, an adaptively dividable dual-port BiTCAM (unifying binary and ternary CAMs) is proposed to achieve a high-throughput, low-power, and low-cost virus-detection processor for mobile devices. The proposed dual-port BiTCAM is realized with the dual-port AND-type match-line scheme which is composed of dual-port dynamic AND gates. The dual-port designs reduce power consumption and increase storage efficiency due to shared storage spaces. Network security for mobile devices is in high demand because of the increasing virus count. Since mobile devices have limited CPU power, dedicated hardware is required, which will be yield by our BitCAM technique is essential to provide sufficient virus detection performance. In this project, an adaptively dividable dualport BiTCAM (unifying binary and ternary CAMs) is proposed to achieve a high-throughput, low-power, and lowcost virus-detection processor for mobile devices. The proposed dual-port BiTCAM is realized with the dual-port AND-type match-line scheme which is composed of dualport dynamic AND gates. The dual-port designs reduce power consumption and increase storage efficiency due to shared storage spaces. Network security for mobile devices is in high demand because of the increasing virus count. Since mobile devices have limited CPU power, dedicated hardware is required, which will be yield by our BitCAM technique is essential to provide sufficient virus detection performance.

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Measuring of Automobile Parameters and its Speed Control

Measuring of Automobile Parameters and its Speed Control
Authors:HANEEF MANSOOR SHAIK, V.PANDU RANGA, K.RAMA RAO

Abstract: The development in Automobiles had made the Automobile systems more complex. The Automobiles today have many electronic units in it to perform a defined task. Though these units are designed to perform accurately, they eventually develop small faults. These faults are to be recognized quickly for proper functioning of the vehicle. These units should be monitored and check continuously for smooth functioning of the vehicle. This requires a advanced diagnostic technology to detect the fault quickly and intimate them. This paper discusses about advanced method of monitoring the condition of the vehicle and also giving intimation if there occurs any fault in the automobile system. This paper gives the advanced communication between the units which monitor the parameters in the vehicle using the fast and reliable communication technology. This paper proposes a effective communication technology for short range communication like in automobiles. The proposed method can also be easily implemented and is also easily configurable. This method uses a combination of both hardware and software which is easy to implement and is also cost effective. 

Keywords: Control Area Network, ECU (Electronic Control Unit), ARM CORTEX M3, Temperature Sensor, Level Sensor, LDR (Light Dependent Resistor). 

INTRODUCTION 

         Electronic Control Unit(ECU) a generic term for any embedded system that controls one or more of the electrical systems or subsystems in a motor vehicle. ECU is a combination of both hardware and software called the firmware. The firmware is a combination of Microcontroller hardware and the embedded software. The each ECU in vehicle performs a specific task defined to it. The electronic control unit that controls a series of actuators on an internal combustion engine to ensure optimal engine performance. It does this by reading values from a multitude of sensors within the engine. Types of ECU include electronic/engine control module (ECM), transmission control module (TCM), brake control module (BCM), central control module (CCM), central timing module (CTM), general electronic module (GEM), body control module (BCM), suspension control module (SCM), control unit, or control module. Taken together, these systems are sometimes referred to as the car's computer. The earlier systems in the automobiles used analog circuitry to perform the tasks like temperature measurement, level sensing. These analog systems were more bulky and consume more space which became difficult to be used in all vehicles. 

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An Efficient Decoding Architecture with Improved Error Correcting Technique for NAND Flash Memory

An Efficient Decoding Architecture with Improved Error Correcting Technique for NAND Flash Memory
Authors:S.NARKISH HASHMA, S.SARANYA DEVI

Abstract: In this project, Due to higher integration densities, technology scaling and variation in parameters, the performance failures may occur for every application. The memory applications are also prone to single event upsets and transient errors which may lead to malfunctions. This paper proposed a novel error detection and correction method using EG-LDPC. This is useful as majority logic decoding can be implemented serially with simple hardware but requires a large decoding time. For memory applications, this increases the memory access time. The method detects whether a word has errors in the first iterations of majority logic decoding, and when there are no errors the decoding ends without completing the rest of the iterations. Also, errors affecting more than five bits were detected with a probability very close to one. Error commonly occurs in the Flash memory while employing LDPC decoding. The SRMMU actually suggests to use a the VTVI design by introducing the Context Number register, however also a PTPI or VTPI design could be implemented that complies to the SRMMU standard. The VTVI design with a physical write buffer and a combined I/D Cache TLB is the most simple design to implement. This will give error correction in minimum cyclic period using LDPC method. In this work, we proposed CLC combine with FAB and BPLRU to further improve the overall system performance by working with virtual memory management collaboratively. Here we proposed new management schemes for VM as well as VIVT cooperatively for flash memory based systems to reduce write activities and to improve I/O performance. In this architecture, we implement WBCLRU and PCLRU for VM Management and VIVT management respectively with LDPC method. And to reduce the complexity compare to the existing architecture. 

Keywords: Bose–Chaudhuri–Hocquenghem (BCH), Bit-Error Rate (BER), Cell-To-Cell Interference (CCI), Multilevel Cell (MLC).

 INTRODUCTION 

         Error correction codes are commonly used to protect memories from so called soft errors, which change the logical value of memory cells without damaging the circuit. As technology scales, memory devices become larger and more powerful error correction codes are needed. To this end, the use of more advanced codes has been recently proposed. These codes can correct a larger number of errors, but generally require complex decoders. To avoid a high decoding complexity, the use of one step majority logic decodable codes was first proposed in for memory application. One step majority logic decoding can be implemented serially with very simple circuitry, but requires long decoding times. In a memory, this would increase the access time which is an important system parameter. Only a few classes of codes can be decoded using one step majority logic decoding. Among those are some Euclidean geometry low density parity check (EG-LDPC) and difference set low density parity check (DS-LDPC) codes.

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A Novel Key Management Technique for Secure Transmission to Remote Cooperative Groups

A Novel Key Management Technique for Secure Transmission to Remote Cooperative Groups
Authors:B. SIVANARAYANA, S. THULASI KRISHNA

Abstract: The most recently developed networks are facing difficulty of efficiently and securely broadcasting to distant cooperative groups. A real confront in working out with such frameworks is to beat the hindrances of the conceivably restricted correspondence from the gathering to the sender, the inaccessibility of a completely trusted key generation center, and the motion of the sender. The current key administration ideal models can't manage these difficulties viably. In this paper, we go around these hindrances and overcome this obstacle by proposing a novel key administration ideal model. The new ideal model is a half and half of conventional show encryption and group key agreement. In such a framework, every part keeps up a solitary public or secret key pair. The rivals or unauthorized individuals can’t read or find any valuable information from the transmitted messages, even if they collude. Both the computation overhead and the communication cost are independent of the group size, after the public group encryption key is extracted. Moreover, our plan encourages straightforward yet proficient member addition or deletion and adaptable rekeying procedures. Its security against conspiracy, its consistent overhead, and its execution invitingness without depending on a completely trusted party render our convention an extremely effective solution to numerous applications. 

Keywords: Key Management, Broadcasting, Ad Hoc Networks, Member Organization, Rekeying. 

INTRODUCTION 

         A wireless ad hoc network system is a decentralized sort of remote system. The system is specially appointed in light of the fact that it doesn't depend on a previous framework, for example, switches in wired systems or access focuses in oversaw remote systems. Rather, every hub partakes in directing by sending information for different hubs, so the determination of which hubs forward information is made alertly on the premise of system network. Notwithstanding the excellent steering, impromptu systems can utilize flooding for sending the information. A specially appointed system ordinarily alludes to any set of systems where all gadgets have approach status on a system and are allowed to connect with some other impromptu system gadget in connection range. It by and large means an answer intended for a particular issue or assignment, non-generalizable, and not proposed to have the capacity to be adjusted to different purposes. Every gadget in a MANET is allowed to move autonomously in any course, and will along these lines change its connections to different gadgets habitually. Every must forward movement disconnected to its own particular utilization, and in this manner be a switch.

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A Tracking System using Location Prediction and Dynamic Threshold for Minimizing SMS Delivery

A Tracking System using Location Prediction and Dynamic Threshold for Minimizing SMS Delivery
Authors:BIRAJDAR SAMEER LALSAHEB, G. SOBHA

Abstract: In this paper, a novel method called location-based delivery (LBD), which combines the short message service (SMS) and global position system (GPS), is proposed, and further, a realistic system for tracking a target’s movement is developed. LBD reduces the number of short message transmissions while maintaining the location tracking accuracy within the acceptable range. The pro-posed approach, LBD, consists of three primary features: Short message format, location prediction, and dynamic threshold. The defined short message format is proprietary. Location prediction is performed by using the current location, moving speed, and bearing of the target to predict its next location. When the distance between the predicted location and the actual location exceeds a certain threshold, the target transmits a short message to the tracker to update its current location. The threshold is dynamically adjusted to maintain the location tracking accuracy and the number of short messages on the basis of the moving speed of the target. The experimental results show that LBD, indeed, outperforms other methods because it satisfactorily maintains the location tracking accuracy with relatively fewer messages. 

Keywords: Global Positioning System (GPS), Location Tracking, Mobile Phones, Prediction Algorithms, Short Message Service (SMS).

 INTRODUCTION 

             The global position system (GPS) has become a common functionality in handheld devices, and therefore, several location-tracking applications have been developed [2]– [15], including continuous location- tracking of elders and children for safety reasons or to prevent them from being lost [2], [3], car monitoring and tracking [4]–[6], and intelligent transportation systems [7]. The GPS is used to obtain the location information of a tar-get (e.g., a mobile device). However, most of the above-cited works used either an 802.11 wireless network or the short message service (SMS) to transmit the location information of a target to a tracker. For example, Lee et al. proposed a real-time location tracking system [2] for childcare or elderly care applications. It transmits the location information of the mobile device to a central GPS application server through the 802.11 wireless networks. This application allows the server to simultaneously monitor multiple targets (e.g., elders or children).  

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Grid Interconnection of Renewable Energy Sources at the Distribution Level with Power-Quality Improvement Features

Grid Interconnection of Renewable Energy Sources at the Distribution Level with Power-Quality Improvement Features
Authors:P. ABHINAV, N. BHOOPAL

Abstract: Renewable energy resources (RES) are being increasingly connected in distribution systems utilizing power electronic converters. This paper presents a novel control strategy for achieving maximum benefits from these grid-interfacing inverters when installed in 3-phase 4-wire distribution systems. The inverter is controlled to perform as a multi-function device by incorporating active power filter functionality. The inverter can thus be utilized as: 1) power converter to inject power generated from RES to the grid, and 2) shunt APF to compensate current unbalance, load current harmonics, load reactive power demand and load neutral current. All of these functions may be accomplished either individually or simultaneously. With such a control, the combination of grid-interfacing inverter and the 3-phase 4-wire linear/non-linear unbalanced load at point of common coupling appears as balanced linear load to the grid. This new control concept is demonstrated with extensive MATLAB/Simulink simulation studies and validated through digital signal processor-based laboratory experimental results. 

Keywords: Active Power Filter (APF), Distributed Generation (DG), Distribution System, Grid Interconnection, Power Quality (PQ), Renewable Energy.  

INTRODUCTION 

      Electric utilities and end users of electric power are becoming increasingly concerned about meeting the growing energy demand. Seventy five percent of total global energy demand is supplied by the burning of fossil fuels. But increasing air pollution, global warming concerns, diminishing fossil fuels and their increasing cost have made it necessary to look towards renewable sources as a future energy solution. Since the past decade, there has been an enormous interest in many countries on renewable energy for power generation. The market liberalization and government’s incentives have further accelerated the renewable energy sector growth. Renewable energy source (RES) integrated at distribution level is termed as distributed generation (DG). The utility is concerned due to the high penetration level of intermittent RES in distribution systems as it may pose a threat to network in terms of stability, voltage regulation and power-quality (PQ) issues. Therefore, the DG systems are required to comply with strict technical and regulatory frameworks to ensure safe, reliable and efficient operation of overall network. With the advancement in power electronics and digital control technology, the DG systems can now be actively controlled to enhance the system operation with improved PQ at PCC. 

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