Time and Power Optimized Enhanced Serial Communication Links for High Throughput Applications

Time and Power Optimized Enhanced Serial Communication Links for High Throughput Applications
Authors:SAROJA, DR.V.SAILAJA

Abstract: This paper proposes embedded transition inversion (ETI) to reduce bit transitions in serializing parallel buses, implies reduction in power. This paper proposes an embedded transition inversion (ETI) coding scheme that uses the phase difference between the clock and data in the transmitted serial data to tackle the problem of the extra indication bit. The technique is implemented in an optimized fashion using pipelining so that it can be used in practical systems with only a slight compromise in performance. This is achieved by calculating the decision as the data is being loaded on to the buffer and doing the encoding on the fly. This is one aspect which is lacking in most existing algorithms as they are not amenable to low delay implementation. 

Keywords: Embedded Transition Inversion (ETI), (Transition Inversion Coding) TIC, Phase Encoding, Tackle, B2I (Bit2invertion), Buffer, Serialized Buffer, Pipelining, Optimization. 

INTRODUCTION 

          Low power design, in a system perspective, happens at all levels of the digital electronic system stack. It is being done from the lowermost device level design to the topmost software design. And there are the intermediate levels where a lot of effort is being expended to make systems run at low power, keeping the compromise in performance to be minimum. The increasing density of the integrated circuits as postulated by Moore’s law makes it even more important to have low power systems since the power supply for such a dense integrated circuit may not keep track in size with the miniaturization of the electronic components. Hence research is being made at all levels of a system stack. A system can consist of multiple components. 

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