An Efficient Decoding Architecture with Improved Error Correcting Technique for NAND Flash Memory

An Efficient Decoding Architecture with Improved Error Correcting Technique for NAND Flash Memory
Authors:S.NARKISH HASHMA, S.SARANYA DEVI

Abstract: In this project, Due to higher integration densities, technology scaling and variation in parameters, the performance failures may occur for every application. The memory applications are also prone to single event upsets and transient errors which may lead to malfunctions. This paper proposed a novel error detection and correction method using EG-LDPC. This is useful as majority logic decoding can be implemented serially with simple hardware but requires a large decoding time. For memory applications, this increases the memory access time. The method detects whether a word has errors in the first iterations of majority logic decoding, and when there are no errors the decoding ends without completing the rest of the iterations. Also, errors affecting more than five bits were detected with a probability very close to one. Error commonly occurs in the Flash memory while employing LDPC decoding. The SRMMU actually suggests to use a the VTVI design by introducing the Context Number register, however also a PTPI or VTPI design could be implemented that complies to the SRMMU standard. The VTVI design with a physical write buffer and a combined I/D Cache TLB is the most simple design to implement. This will give error correction in minimum cyclic period using LDPC method. In this work, we proposed CLC combine with FAB and BPLRU to further improve the overall system performance by working with virtual memory management collaboratively. Here we proposed new management schemes for VM as well as VIVT cooperatively for flash memory based systems to reduce write activities and to improve I/O performance. In this architecture, we implement WBCLRU and PCLRU for VM Management and VIVT management respectively with LDPC method. And to reduce the complexity compare to the existing architecture. 

Keywords: Bose–Chaudhuri–Hocquenghem (BCH), Bit-Error Rate (BER), Cell-To-Cell Interference (CCI), Multilevel Cell (MLC).

 INTRODUCTION 

         Error correction codes are commonly used to protect memories from so called soft errors, which change the logical value of memory cells without damaging the circuit. As technology scales, memory devices become larger and more powerful error correction codes are needed. To this end, the use of more advanced codes has been recently proposed. These codes can correct a larger number of errors, but generally require complex decoders. To avoid a high decoding complexity, the use of one step majority logic decodable codes was first proposed in for memory application. One step majority logic decoding can be implemented serially with very simple circuitry, but requires long decoding times. In a memory, this would increase the access time which is an important system parameter. Only a few classes of codes can be decoded using one step majority logic decoding. Among those are some Euclidean geometry low density parity check (EG-LDPC) and difference set low density parity check (DS-LDPC) codes.

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