FIR High Speed VLSI Design for Area Efficient Parallel Digital Filter Structure for Low Power CMOS Voltage Mode SRAM Cell

FIR High Speed VLSI Design for Area Efficient Parallel Digital Filter Structure for Low Power CMOS Voltage Mode SRAM Cell
Authors:PADMA SILIVERI

Abstract: In this paper we propose a novel design of a low power static random access memory (SRAM) cell for high speed operations. The model adopts the voltage mode method for reducing the voltage swing during the write operation switching activity. Dynamic power dissipation increases when the operating frequency of the SRAM cell increases. In the proposed design we use two voltage sources connected with the Bit line and Bit bar line for reducing the voltage swing during the write “0” or write “1” operation. We use 90 nm CMOS technology with 1 volt of power supply. Simulation is done in Micro wind 3.1 by using BSim4 model. Dynamic power for different frequencies is calculated. We compare it with conventional 6-T SRAM cell. The simulation results show that the power dissipation is almost constant even the frequency of the proposed SRAM model increases. This justifies the reduction of the dynamic power dissipation for high frequency CMOS VLSI design. 

Keywords: CMOS; Dynamic Power; SRAM; Voltage Mode; Voltage Swing. 

 INTRODUCTION 

      In today’s technology advancement world, Reduction of power consumption makes a device more reliable. The need for devices which dissipate minimum amount of power was a major driving force behind the development of CMOS technologies. Consequently, CMOS devices are best known for low power consumption. However, for minimizing the power requirements for a system, by knowing that CMOS devices may use less power than equivalent devices from other technologies does not do enough [1]. For high speed systems, Low power design has become an essential issue in VLSI design [2]. Normally, dynamic power dissipation dominates in most digital systems. Dynamic power dissipation depends on the switching frequency, supply voltage, and the output voltage swing. Reduction in the supply voltage is the most efficient approach to minimize the dynamic power dissipation. Unfortunately, lower supply voltage leads to degradation in performance dramatically [3]. Lower supply voltage decreases the threshold voltage which will increase the sub-threshold current or leakage current hence the static power dissipation increases. Also by Limiting the output voltage swing, dynamic power and delay can be reduced.

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