High Secured and Low Power Crypto Core Design using BIST

High Secured and Low Power Crypto Core Design using BIST
Authors:K.HARSHA HEMANTHA LAKSHMI, JAGAN MOHAN RAO S

Abstract: The main motive of this project is to design a crypto device with low complexity and high security by using “Advanced AES” Algorithm along with BIST technique. The selective application of technological and related procedural safeguards is an important responsibility of every Federal organization in providing adequate security to its electronic data systems and coming to BIST concept there are two main functions that must be performed on-chip in order to implement builtin self-test (BIST): test pattern generation and output response analysis. The most common BIST schemes are based on pseudorandom test pattern generation using linear feedback shift registers (LFSR’S) and output response compaction using signature analyzers. To accomplish high security for a system we are using the crypto devices technique in our project. 

Keywords: Cryptography, BIST, LFSR, AES, TPG, SA.

INTRODUCTION 

      Most of the user now a day’s using wireless communication for fast sending and receiving the mails in less time and in less cost. When this way of communication is going on, the unauthorized people who have the intension to know about our conversion will hack the information within that frequency. After hacking the information the hacker can know about what we are discussing. This leads to leakage of information. Nowadays, secure circuits are commonly used for applications such as e-banking, pay tv, cell phone... Because they hold personal data and must process secure operations, security requirements such as source/sink authentication, data integrity, confidentiality, or tamper resistance are maintained by means of several dedicated components. Confidentiality is ensured through cryptographic mechanisms generally implemented on coprocessors. These mechanisms encode/decode plaintexts/ cipher texts with the help of secret keys that must be preserved from compromise. Testing a secure circuit requires a specific attention since any undetected malfunction may induce a vulnerability and any extra test mechanism may induce new security vulnerabilities. For instance, generation of deterministic test patterns and design for testability such as scan design provide very high fault coverage. 

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